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Uwe Meyer-Baese

Uwe Meyer-Baese

Associate Professor, Electrical and Computer Engineering, Florida State University

Phone: (850) 410-6479

2525 Pottsdamer Street
Tallahassee, FL 32310



Ph.D. , Darmstadt University of Technology, 1995

Research Interests:

Dr. Meyer-Baese is an Associate Professor at the FAMU-FSU College of Eng., Florida State University, Tallahassee, USA. His area of research include: Real-time signal processing, biomedical image and signal processing, VLSI for wireless communication systems, multimedia, digital signal processing with FPGAs, and Quantum Computing. From 1998-2000 he worked in the ASIC industry developing the next generation DSP ASIC Technology for VLSI Technology, now part of Philips. He was postdoctoral fellow at University of Florida, Gainesville, USA, 1996-1998, to develop a generic RNS ASIC library and design of 2D wavelet processor for the European Space Agency. From 1989-1995 he was a research assistant, Department of Electrical Engineering, Darmstadt University of Technology, Germany, for the development of full digital receivers in FPGA technology. He holds 3 patents, has published over 80 journal and conference papers, and supervised more than 60 master thesis projects in the real-time DSP/FPGA area. In 2003, he was awarded the “Habilitation” (venia legendi) by the Darmstadt University of Technology. He is author of the best selling Springer textbook on DSP with FPGAs. He received in 1997 the Max-Kade Award in Neuroengineering and the Humboldt Research Award in 2005. Dr. Meyer-Baese is a IEEE, BME, SP and C&S society member.

Publications List:

  • U. Meyer-Baese. Digital Signal Processing with Field Programmable Gate Arrays, 775 pages. 3. Edition. ISBN: 978-3-540-72612-8 Springer-Verlag, Berlin, 2007.
  • Uwe Meyer-Bäse, Hariharan Natarajan, and Andrew G. Dempster, “Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique,” EURASIP Journal on Advances in Signal Processing, vol. 2007, Article ID 67360, 8 pages, 2007. doi:10.1155/2007/67360.
  • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla, and A. Lloris, “IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pages 578-591, Vol. 15, No. 5, May 2007.
  • U. Meyer-Baese Hariharan Natarajan, Encarnacion Castillo, and Antonio García. “Faster than the FFT: The chirp-z RAG-n Discrete Fast Fourier Transform,” Frequenz, Vol. 60, pages 147-151, July/August 2006.